1. Field of the Invention
The present invention generally relates to a reset device and more particularly to a reset device outputting a reset signal in accordance with the magnitude of an input power supply voltage.
2. Description of the Related Art
Conventionally, there have been known circuits for generating a reset signal in which a reset signal is generated based on a change of power supply voltage and an initial setting of a system is performed so as to prevent malfunction of a device resulting from an indefinite state of an output logic upon power-on operation of a system on which a CMOS logical circuit such as a flip-flop is mounted (refer to Patent Document 1, for example).
FIG. 1 is a diagram showing a conventional circuit for generating a reset signal. The reset signal generating circuit shown in FIG. 1 includes N-channel MOS transistors 110 and 120, a resistor 130, an inverter 150, an OR operator 180, and an RS flip-flop 190. The inverter 150 is constructed as a CMOS inverter and includes a P-channel MOS transistor 160 and an N-channel MOS transistor 170.
In FIG. 1, when a power supply voltage VDD is applied from an input terminal, a voltage VN1 of a node N1 is expressed as VDD-2VTH divided using the resistor 130, where threshold voltages of the N-channel MOS transistors 110 and 120 are VTH. On the other hand, thresholds of the P-channel MOS transistor 160 and the N-channel MOS transistor 170 correspond to those of N-channel MOS transistors 110 and 120, respectively, so that a threshold voltage VTH1 of the inverter 150 is VDD/2. When the voltage VN1 of the node N1 is larger than the threshold voltage VTH1 of the inverter 150, the N-channel MOS transistor 170 conducts and outputs an L-level reset signal. By contrast, when the voltage VN1 of the node N1 is smaller than the threshold voltage VTH1 of the inverter 150, the P-channel MOS transistor 160 conducts and outputs an H-level reset signal.
FIGS. 2A and 2B are waveform charts illustrating operation of a reset signal generating circuit corresponding to the conventional technique shown in FIG. 1. In FIG. 2A, LA indicates a temporal change of the power supply voltage VDD and LB indicates a temporal change of the node voltage VN1. Further, VTH1 indicates the threshold voltage of the inverter 150. In this case, the threshold voltage VTH1 of the inverter 150 changes at a half of the temporal change LA of the power supply voltage VDD and when the node voltage VN1 does not exceed the threshold voltage VTH1 of the inverter 150, a reset signal R is output at the H level. Then, when the node voltage VN1 exceeds the threshold voltage VTH1 of the inverter 150, the reset signal R is output at an L level. Further, when the reset signal R is output at the H level, the RS flip-flop 190 is reset and when the reset signal R is output at the L level, logic is maintained.
By constructing in this manner, the reset signal R is output at the H level until the power supply voltage VDD becomes twice the threshold voltage VTH of the N-channel MOS transistors 110 and 120.
Patent Document 1: Japanese Laid-Open Patent Application No. 9-181586
However, in the structure disclosed in above-mentioned Patent Document 1, the inverter 150 may be subject to malfunction when the power supply voltage is rapidly changed.
FIGS. 3A, 3B, 3C, and 3D are diagrams illustrating problems of a CMOS inverter 150a according to the conventional technique. FIG. 3A shows a configuration of the conventional CMOS inverter 150a. In FIG. 3A, the CMOS inverter 150a includes a P-channel MOS transistor 160a and an N-channel MOS transistor 170a. An input VIN is constructed as a common gate an output Vout is constructed as a common drain. A source of the N-channel MOS transistor 170a is connected to a ground line and a source of the P-channel MOS transistor 160a is connected to a power supply voltage VDD line. The CMOS inverter 150a is constructed such that when a voltage at the H level is input to the VIN, the N-channel MOS transistor 170a conducts and outputs at the L level, and when a voltage at the L level is input to the VIN, the P-channel MOS transistor 160a conducts and outputs at the H level.
The following describes a case where the power supply voltage VDD shown in FIG. 3B is input to the CMOS inverter 150a constructed in this manner. FIG. 3B shows a case where the power supply voltage VDD is input at a substantially constant voltage and a rapid voltage change is generated due to a sudden voltage change at the power supply voltage. In this case, as shown in FIG. 3C, the input voltage VIN of the CMOS inverter 150a is raised due to capacity coupling following the rapid change of the power supply voltage. When the value exceeds a threshold Vth=VDD/2 of the CMOS inverter 150a, as shown in FIG. 3D, the Vout required to be maintained at the H level is changed to be at the L level under the influence of the VIN exceeding the threshold. In this manner, the configuration shown in FIG. 3A poses problems in that the CMOS inverter 150a may be subject to malfunction due to the rapid change of the power supply voltage.